Technical Field
The disclosure in generally relates to a semiconductor device and method for fabricating the same, and more particularly to a fin field-effect transistor (FinFET) and method for fabricating the same.
Description of the Related Art
As the evolution of semiconductor process, technology node has progressed into nanometer-scale phenomena, a semiconductor device with higher functional density is provided. However, the critical sizes and features dimension of the semiconductor device are simultaneously shrunk small enough to make it challenging to produce a semiconductor device with the advantages of higher functional density without deteriorating the device performance. For overcoming the challenge, a semiconductor device with a three-dimension design, such as a FinFET, is provided.
A FinFET is typically made by steps as follows: A portion of a silicon layer disposed on a substrate is removed by an etch process to form a vertical fin protruding from a surface of the substrate. A gate structure is then provided covering on a top surface and sidewalls of the vertical fin to form a channel in the vertical fin, thereby an active region expending form the top surface to the sidewalls of the vertical fin can be defined. In addition, a strained silicon/silicon-germanium (Si/SiGe) strained source/drain may be formed in the vertical fin adjacent to the gate structure by an optional epitaxial growth process in order to improve the carrier mobility of the FinFET.
However, there are still many challenges to satisfy the stringent requirement for fabricating a FinFET with decreasing feature sizes. For example, during the process for fabricating the FinFET, the scale (size) and the accuracy of components may be deteriorated due to the over etch of the vertical fin and the spacer material while a gate spacer is formed on sidewalls of the gate structure, and whereby the yield and quality of the FinFET is adversely affected by the loss of the vertical fin and the spacer material.
Therefore, there is a need of providing an improved semiconductor device and method for fabricating the same to obviate the drawbacks encountered from the prior art.